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| VLSI - Design & Verificatiion engineer
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| i am looking out for a job in Design and verification in the field of Soc , FPGA
Expertise in:
1.Front-end Verification.
2.Directed Test Bench Verification approach.
Exposure on:
1.Verification Methodology Manual(VMM)
2.Formal verification.
Languages:
HDL : Verilog,VHDL
HDVL : System Verilog
Scripting Languages : Perl
Tools:
Simulation : VCS,Axiom, ModelSim
Synthesis :Xilinx,
Leonardo
spectrum
Validation Board : Virtex E
Methodology Exposure : VMM
Platform : Linux,Windows.
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| Resume reference: | reLy8MfO | |
| Date last updated: | 6 October 2008 | |
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| Education: | Post-graduate degree - Msc - electronics | |
| Experience: | 2 years | |
| Employment situation: | In permanent employment | |
| Salary expectations: | as per industry standards | |
| Availability: | From 27 October 2008 | |
| Type of employment: | Full Time, Part Time, Temporary, Home Based | |
| Location: | Abroad - India | |
| Looking to work in: | Nationwide | |
| Age: | 26 | |
| Gender: | Male | |
| Marital status: | Single | |
| Own transport: | Yes | |
| Driver's license: | Yes | |
| Citizenship: | Indian | |
| Right to work | No, I need sponsorship | |
| English level: | Intermediate | |
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